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datasheet R1EX24128BSAS0A r1ex24128btas0a r10 d s0 006e j01 0 0 rev.1.00 a ug. 04, 201 0 two-wire serial interface 128k eeprom (16-kword 8-bit) description r1ex 2 4 x x x se ries are tw o- wire se rial interfa ce eepr o m ( e lectrically erasable a n d pr ogramm able rom). they realize h i gh speed , l o w power con s u m p tio n an d a h i gh lev e l of reliab ility by e m p l o y in g ad v a n c ed m o nos m e m o ry t echn o l o gy an d c m os p r oces s an d l o w v o l t a ge ci rc ui t r y t echn o l o gy . t h ey al so ha ve a 6 4 - by t e page p r o g ram m i ng fun c tion to m a k e th ei r write op eration faster. note: renesas electronics ? se ri al e e prom a r e a u thorized for usi n g cons um er ap p licatio ns su ch as cellu lar p h o n e , ca m c orde rs, audio e q uipm ent. t h ere f ore, pl ease co ntact renesas electronics? sales o ffi ce be fo re usin g industrial applications s u c h as autom o tive sy st em s, em bedd ed c ont rol l e rs , and m e t e rs. features ? si ngl e su p p l y : 1. 8 v t o 5. 5 v ? two-wire se ria l interface (i 2 c s e r i a l b u s) ? c l ock fre q u enc y : 40 0 k h z ? po wer di ssi pat i on: ? stan db y: 2 a (m ax) ? active (read ): 1 m a (m ax) ? active ( write): 3 . 0 m a (m ax) ? a u t o m a t i c p a ge wr ite: 64 -b yte/p a g e ? write cycle time: 5 m s ? endurance: 1,000k cycles @ 25 c ? data reten tio n : 100 years @ 2 5 c ? sm a ll size p ack ag es: sop-8p in , tssop-8 p in ? shipping ta pe and reel ? tss o p 8- pi n: 3, 00 0 ic / r eel ? sop 8 - pi n: 2, 50 0 ic / r eel ? tem p erature ra nge: ? 40 to +85 c ? lead f r e e pr odu cts. r10ds 0 0 06ej 010 0 rev.1.00 page 1 of 1 6 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a ordering information ty pe no. inte rna l orga n i za tion op eratin g v o ltag e fre que nc y pack ag e r1e x 2 412 8bs as0a 128k b i t (1638 4 8-bit) 1.8 v to 5.5 v 400 khz 150 mil 8-pi n pl astic sop prsp0008df- b (fp-8dbv) lea d free r1e x 2 412 8bt as0a 128k b i t (1638 4 8-bit) 1.8 v to 5.5 v 400 khz 8-pin plastic t ssop pt sp0008jc- b (t t p -8dav) lea d free pin arrangement /8-pin tssop 1 2 3 4 8 7 6 5 a0 a1 a2 v ss v cc wp scl sda (top view) 8-pin sop pin description pin na me func tio n a0 to a2 device addr es s scl serial cl ock in p u t sda serial d a ta in p u t/output w p w r i t e p r o t e c t v cc p o w e r su ppl y v ss g r o u n d block diagram control logic high voltage generator address generator x decoder y decoder memory array y-select & sense amp. serial-parallel converter v cc v ss wp a0, a1, a2 scl sda r10ds 0 0 06ej 010 0 rev.1.00 page 2 of 1 6 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a absolute maximum ratings para mete r s y m b o l v a l u e u n i t supp l y v o ltag e relative to v ss v cc ? 0.6 to +7.0 v input voltag e relative to v ss v i n ? 0.3 to v cc +0 .3 v operatin g temperatur e rang e * 1 t o p r ? 40 to + 85 c storage temp e r ature ran ge t s tg ? 55 to + 125 c notes: 1. includi ng el e c trical c haract e ristics and d a ta retention. dc operating conditions pa rame t e r s y m b o l m i n ty p ma x u n i t supp l y v o ltag e v cc 1 . 8 5 . 5 v v ss 0 0 0 v input hig h volta ge v ih v cc 0.7 v cc + 0.3 v input lo w vo lta ge v il ? 0.3 v cc 0.3 v operatin g temperatur e t opr ? 40 + 8 5 c dc characteristics (ta = ? 40 to +8 5 c, v cc = 1. 8 v t o 5 . 5 v ) pa rame t e r s y m b o l m i n ty p ma x u n i t te s t c onditi o n s input leak ag e current i li 2 . 0 a v cc = 5.5 v, vi n = 0 to 5.5 v output leaka g e current i lo 2 . 0 a v cc = 5.5 v, vout = 0 to 5.5 v standb y v cc c u rrent i sb 1 . 0 2 . 0 a vin = v ss or v cc read v cc curr ent i cc1 1 . 0 m a v cc = 5.5 v, r ead at 40 0 khz write v cc current i cc2 3 . 0 m a v cc = 5.5 v, write at 400 khz output lo w volt age v ol2 0 . 4 v v cc = 2.7 to 5.5 v, i ol = 3.0 ma v ol1 0 . 2 v v cc = 1.8 to 2.7 v, i ol = 1.5 ma capacitan ce (ta = +2 5 c, f = 1 mh z ) pa rame t e r s y m b o l m i n ty p ma x u n i t te s t c onditi o n s input capac itan ce (a0 to a2, scl, w p ) cin * 1 6.0 pf vin = 0 v output capacit ance (sda) c i/o * 1 6.0 pf vout = 0 v note: 1. not 100 % tested. memor y cell characteristics (v cc = 1.8 v to 5 . 5 v ) t a =2 5 c t a =8 5 c n o t e s endur ance 1,000k c y c l es min. 100k c y cl es mi n 1 data retenti on 100 ye ars min. 10 years mi n. 1 notes: 1. not 100 % tested r10ds 0 0 06ej 010 0 rev.1.00 page 3 of 1 6 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a ac characteristics (ta = ? 40 to +8 5 c, v cc = 1. 8 t o 5 . 5 v ) test conditions ? inpu t pu les levels: ? v il = 0. 2 v cc ? v ih = 0. 8 v cc ? inpu t rise and fall ti me: 20 ns ? inpu t and ou tpu t ti m i n g referen ce lev e ls: 0.5 v cc ? o u t p u t l o ad : ttl g a te + 100 p f pa rame t e r s y mbol m i n ty p ma x u n i t note s clock freq uenc y f sc l ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? % r10ds 0 0 06ej 010 0 rev.1.00 page 4 of 1 6 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a timing wa veforms bus timing t f 1/f scl t high t su .st a t hd .st a t hd .d a t t su .d a t t su .st o t bu f t dh t aa t lo w t r scl wp sd a (in) sd a (out) t su .wp t hd .wp scl sd a d0 in wr ite data a c k (address (n)) t wc (inter nally controlled) stop condition star t condition write c y cle timing r10ds 0 0 06ej 010 0 rev.1.00 page 5 of 1 6 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a pin function serial clock (scl ) th e scl p i n is u s ed t o co n t rol serial in pu t/ou t pu t d a ta tim i n g. th e scl i n pu t is u s ed to p o sitiv e edg e clo c k d a ta in t o eepr o m de vi ce an d negat i v e ed ge cl oc k d a t a out o f eac h devi ce. m a xi m u m cl ock rat e i s 4 0 0 khz . serial input/outpu t data (sda) the sd a pi n i s bi di rect i onal fo r se ri al dat a t r ans f er . the s d a pi n need s t o be pul l e d u p by resi st or a s t h at pi n i s o p en - drai n dri v e n st r u ct u r e. use p r ope r resi st o r v a l u e f o r y o u r s y st em by consi d eri n g v ol , i ol an d t h e s d a pi n ca paci t a nc e. ex cep t fo r a st art cond itio n an d a st o p cond itio n wh ich will b e d i scu ssed l a ter, th e sda tran sition n eeds to b e co m p lete d du ri n g t h e sc l l o w peri o d . da ta validit y (sda d a ta c h ange tim i n g w a v e form ) scl sd a data change data change note: high -to-l o w a nd low-to-hig h cha nge of sda sho u ld b e done d u ri ng the scl low peri od. dev i ce addr ess (a0, a1, a2) ei ght de vi ces c a n be wi re d f o r o n e c o m m on dat a b u s l i n e as m a xim u m . devi ce ad d r ess p i ns are u s ed t o di st i n g u i s h each device a n d device a d dre ss pi ns s h oul d be c o nnected to v cc or v ss . whe n de vi ce a d d r ess co de pr ovi ded f r om sda pi n m a t c hes co rres p on di n g ha rd -wi r ed de vi c e ad dres s pi ns a0 t o a 2 , t h at one de vi ce ca n be act i v at e d . pin connec t ions for a0 to a2 pin co nn ection memo r y size max co n n ect n u m b e r a 2 a 1 a 0 no te 128k b i t 8 v cc /v ss * 1 v cc /v ss * 1 v cc /v ss * 1 note: 1. durin g floati ng, ?v cc /v ss ? are fixed to v ss . write pro t ec t (wp ) whe n t h e wri t e pr ot ect pi n ( w p ) i s hi g h , t h e w r i t e pr ot ect i o n feat ure i s en abl e d a n d ope r a t e s as s h o w n i n t h e f o l l o wi n g tab l e. also , ack nowledg m e n t "0 " is o u t p u t t e d after inpu ttin g d e v i ce ad dress and m e m o ry ad dress. after inpu ttin g writ e dat a , ac kn o w l e dgm ent "1" (n o a c k ) is outp u tted . wh en t h e wp i s low, write o p eratio n fo r all me m o ry arrays are allowe d. the read op e r a tion is al ways activated irres p ective of the wp pin status. write pro t ec t are a w r ite p r o t ect are a w p p i n statu s 128 k b i t v ih f u l l ( 1 2 8 k b i t ) v il normal re ad/ w r ite oper ation r10ds 0 0 06ej 010 0 rev.1.00 page 6 of 1 6 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a functional description start conditi on a h i gh -t o - low tran sitio n of t h e sda with t h e scl h i gh is n eed ed i n o r d e r to start read , write o p e ratio n (see start co nd itio n an d sto p cond itio n ) . stop con d ition a low-to -h igh tran sitio n of t h e sda with t h e scl h i gh is a stop co nd ition . th e stand-by o p e ration starts after a read sequence by a stop condition. in t h e case of write ope ration, a st op condition te rm inates t h e write data inputs a n d place th e d e v i ce in a in tern ally-ti m e d write cycle to th e m e m o rie s . after th e in t e rn ally-ti m ed write cycle which is sp ecified as t wc , the de vice enters a sta n dby m ode (see write cycle timing). start conditi on and stop condition scl sd a (in) stop condition star t condition scl sd a in sd a out 12 8 9 ac kno wledge out ack n o w l e dg e all add r esses an d d a ta wo rd s are serially tran sm it ted to a n d fr om i n 8- bi t wo r d s. t h e re cei ver se n d s a zero t o acknowledge t h at it has recei ved each word. this ha ppens during nint h cl ock cycl e. the transm itter keeps bus ope n t o receive ac knowledgm e nt from the receive r at the ni nth cl oc k. in t h e write operation, e e prom se nds a zero t o acknowledge after receiving every 8-bit words. in t h e read operation, eeprom se nds a zero to acknowledge after receiving t h e device address word. afte r sendi ng read dat a , the eepr o m waits acknowledgm e nt by k eepi n g bus open. if t h e ee prom receives zero as an acknowledge, it sends r ead data of ne xt address. if t h e ee prom receives ack nowledg m e n t "1 " (no ack n o w led g m en t) an d a fo llowing stop co nd itio n, it stop s th e read o p e ration an d en ters a stand-by m ode . if t h e ee pr om recei ves neither ac know ledgm ent "0" nor a stop c o ndi tion, t h e ee pr om keeps bus ope n wi t h out s e ndi ng rea d da t a . ack n o w l e dg e timing wav e form r10ds 0 0 06ej 010 0 rev.1.00 page 7 of 1 6 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a dev i ce addr essing the e e pr om devi ce re qui re s an 8 - bi t devi c e ad dres s wo rd f o l l o wi ng a st art condition t o ena b le the c h i p for a rea d or a wri t e ope rat i o n . t h e de vi ce a d d r ess w o r d c o nsi s t s of 4 - bi t devi ce c o de, 3 - bi t de vi ce ad d r ess co de a n d 1- bi t read / w rite(r/w) cod e . th e m o st sig n i ficant 4 - b it of th e de v i ce addr ess w o rd ar e used to d i stin gu ish dev i ce typ e an d t h i s eepr o m uses ? 1 01 0? fi xed co de. t h e devi ce a d dres s wo r d i s fol l o w e d by t h e 3 - bi t devi ce a d dres s code i n t h e or der o f a 2 , a 1 , a 0 . t h e de vi ce ad d r ess c o de sel ect s one devi ce o u t o f a l l devi ces w h i c h a r e c o n n ect e d t o t h e b u s. th is m ean s th at th e d e v i ce is selected if th e in pu tted 3-b it d e vi ce ad d r ess c ode i s e qual t o t h e co rre sp o n d i ng ha rd -wi r ed a2-a0 p i n statu s . th e eigh th b it of th e d e vice ad dress word is th e read /write(r/ w) b it. a write o p e ratio n is i n itiate d if th is b it is low an d a read op eratio n is i n itiated if th is b it is h i g h . up on a com p are o f t h e dev i ce address word , t h e eeprom en ters th e read o r write o p e ra tio n after ou tpu ttin g th e zero as an ack nowledg e. th e eeprom tu rn s t o a stand-by state if the de vice c o de is not ?101 0? or d e v i ce addr ess cod e d o e sn ? t co in ci d e w ith statu s of th e co rr esp ond hard-wire d de vice address pi ns a0 t o a2. dev i ce addr ess word de v i c e ad d r es s w o r d (8-b it) de v i ce c ode (fix e d ) de v i ce a ddre s s c ode r/w c ode * 1 1 2 8 k 1 0 1 0 a 2 a 1 a 0 r/w note: 1. r/w = ?1? is read and r/w = ?0? is w r ite. r10ds 0 0 06ej 010 0 rev.1.00 page 8 of 1 6 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a write o p era t ions (w p =lo w ) byte write: (write oper ati o n during w p =low status ) a wri t e ope rat i o n re q u i r es a n 8- bi t de vi ce a d dres s wo rd wi t h r / w = ? 0 ?. the n t h e eep r o m se nds ac kn o w l e d g m e nt "0" at the ni nth clock cycle. after the s e, t h e 128kbit ee pr om recei ves 2 sequence 8-bit me m o ry addr e ss words . upon receipt of t h is me m o ry addre ss, the eepr o m outputs acknowledgm ent "0" a n d r ecei ves a following 8-bit write data. after recei pt of write data, the eepr o m outputs ac knowle dgm en t "0". if the eeprom r eceives a stop condition, the eeprom e n te rs a n inte rnally-ti m ed write cy cle and term inates receipt of sc l, sda inputs until com p letion of the write cycle. t h e ee prom returns to a sta n dby m o d e after co m p letio n of th e write cycle. b y te write o p era t ion de vice address 1st memor y address (n) 2nd memor y address (n) wr ite data (n) 128k 10 10 w a12 a11 a13 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop star t ac k ac k ac k r/w * 1 * 1 note: 1. don't care bit ac k wp note: 1. don't care bit de vice address 1st memor y address (n) 2nd memor y address (n) wr ite data (n+m) wr ite data (n) 128k 10 10 w a12 a11 a13 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d5 d4 d3 d2 d1 d0 stop star t ac k ac k ac k ac k ac k r/w * 1 * 1 wp page write : th e eeprom is cap ab le of the p a g e write o p eratio n wh ich allo ws an y n u m b er o f b y tes u p to 64 b y tes to b e written in a single write cy cle. t h e page write is the sa me seque nce a s th e b y te write ex cep t fo r inpu ttin g t h e m o re write d a ta. the p a g e write is initiated b y a start co nd itio n, d e v i ce address wo rd , m e m o ry a d dress(n) and write d a ta (dn) with ev ery ninth bit ac knowledgm e nt. t h e ee prom e n ters t h e page write ope ration if the eepr o m receives m o re write data (dn+ 1) i n stead of recei ving a stop cond ition. the a 0 to a5 address bits a r e autom a tical ly increm en ted upon receivi ng write data (dn+1). t h e eeprom can cont inue t o receive write data up t o 64 bytes. if t h e a 0 to a5 address bits reac he s th e last add r ess of th e p a g e , the a0 t o a5 ad dress b its will ro l l o v e r t o th e first add r ess of t h e sam e p a g e and p r ev iou s write data will be ove rwritten. upon recei ving a st op c ondition, t h e eepr om stops recei ving write data and e n ters in tern ally-ti m e d write cycle. page write opera t ion r10ds 0 0 06ej 010 0 rev.1.00 page 9 of 1 6 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a write o p era t ions (w p =h igh ) byte write: (write oper ati o n during w p =hi g h st at us ) a wri t e ope rat i o n re q u i r es a n 8- bi t de vi ce a d dres s wo rd wi t h r / w = ? 0 ?. the n t h e eep r o m se nds ac kn o w l e d g m e nt "0" at the ni nth clock cycle. after th e s e, t h e 128kbit ee pr om recei ves 2 sequ ence 8-bit me m o ry addre ss words . upon receipt of this m e m o ry address , the e e prom outputs acknowledgment "0 ". after recei pt of 8-bit write data, the eepro m ou tpu t s ack now ledg m e n t "1 " (n o ac k) . th en t h e eeprom write o p e ratio ns are no t allo wed . b y te write o p era t ion de vice address 1st memor y address (n) 2nd memor y address (n) wr ite data (n) 128k 10 10 w a12 a11 a13 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop star t ac k ac k ac k r/w * 1 * 1 note: 1. don't care bit no a c k wp note: 1. don't care bit de vice address 1st memor y address (n) 2nd memor y address (n) wr ite data (n+m) wr ite data (n) 128k 10 10 w a12 a11 a13 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d5 d4 d3 d2 d1 d0 stop star t ac k ac k no a c k ac k r/w * 1 * 1 wp no a c k page write : th e p a g e write is th e sam e seq u e n ce as th e byte write. th e p a g e write is initiated b y a start co nd itio n, d e v i ce address wo r d a n d m e mory a d dress ( n) wi t h e v ery ni nt h bi t ack no wl e dgm ent " 0". b u t aft e r i n p u t t i ng wri t e dat a (d n) , t h e eepro m ou tpu t s ack now ledg m e n t "1 " (n o ac k ). th en t h e eeprom write o p e ratio ns are no t allo wed . page write opera t ion r10ds 0 0 06ej 010 0 rev.1.00 page 1 0 of 16 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a ackno w ledg e po lling : ackno wled g e p o lling featu r e is u s ed to sh ow if th e eepr o m is in a i n ternally-ti m ed writ e cycle o r no t. th is feature is in itiated b y th e stop co nd itio n after i n pu ttin g write d a ta. this requ ires th e 8 - b it d e v i ce add r ess word fo llo wi n g th e start co nd itio n during a in tern ally-ti m ed write cycle. ackn owledg e p o lling will o p e rate wh en t h e r/ w cod e = ?0 ?. a c kno w l ed g m en t ?1 ? (no ackn ow ledg m e n t ) sho w s th e eep rom is in a intern ally-ti m ed write cycle and ack nowledg m e n t ?0 ? sh ows t h at th e i n tern ally-ti m ed write cycle h a s co mp leted . see write cycle po llin g using ack. write c y cle polling using ack send wr ite command send stop condition to initiate wr ite cycle send star t condition send de vice address w ord with r/w = 0 send memor y address send star t condition send stop condition send stop condition proceed r andom address read oper ation proceed wr ite oper ation ne xt oper ation is addressing the memor y ye s ye s no no ac k retur ned r10ds 0 0 06ej 010 0 rev.1.00 page 1 1 of 16 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a rea d oper ation th ere are th ree read o p e ratio ns: curren t ad dress read , ran dom read , and seq u e n tial read . read o p e ratio ns are i n itiated the sam e way as write operati o ns with th e excep tio n of r/ w = ?1 ?. current addr ess re ad: th e i n tern al add r ess co un ter main tain s the l a st address acc essed duri ng the la st read or write op eration , with increm ented by one . c u rre n t addres s rea d a ccesses the address ke pt by t h e internal address counter. after receiving a start con d ition an d th e d e v i ce ad dress wo rd (r/w is ?1 ?), the eepr o m outp u t s t h e 8 - b it cu rren t add r ess d a ta fro m th e m o st sig n i ficant b it fo llo wi n g ack nowledg m e n t ?0 ?. if the eeprom rece ives ac knowledgm ent ?1? (no ack now ledg m e n t ) and a fo llow i ng stop con d itio n , t h e eepro m st o p s t h e r e ad op er atio n and is t u rn ed t o a stan db y state. in case th e eeprom h a s accessed t h e last ad dress of th e last p a g e at p r ev io us read op erat io n , th e curren t add r ess will roll ove r a n d re turns to zero a d dress . in case the ee prom ha s acces sed the last address of the pa ge at previous write o p e ration , t h e cu rren t add r ess will ro ll ov er with in p a g e add r es sing an d retu rn s to th e first ad dress in t h e sam e p a g e . th e cu rren t add r ess is v a lid wh ile p o wer is o n . th e current ad dress after p o wer o n will b e ind e fin ite. th e rando m read ope rat i o n descr i bed bel o w i s n ecessary t o de f i ne t h e m e m o ry add r ess . curr ent add r ess read o p era t ion 128k de vice address read data (n+1) star t stop 10 10 r d7 d6 d5 d4 d3 d2 d1 d0 ac k no a c k r/w r10ds 0 0 06ej 010 0 rev.1.00 page 1 2 of 16 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a ra nd om re ad : th is is a read op eration with defin e d re a d a d dres s. a ra ndom read require s a dum m y write to set rea d a d dress . t h e eeprom rece ives a sta r t condition, de vice a d d r ess w o r d (r /w = 0 ) a n d m e m o ry addre ss 2 8 - b it seq u e ntiall y. th e eeprom outputs ac knowledgm e nt ?0? afte r recei ving m e m o ry addre ss t h en ente rs a c u rre nt address read with receiving a start condition. the eeprom outputs the rea d data of t h e a d dress which was de fine d in the dumm y write ope ration. after recei ving ac knowledg m e nt ?1? ( no ac knowledgm e nt) and a followi ng stop c o ndition, t h e eeprom stops the ra ndom read operation and returns to a sta n dby st ate. rand om rea d opera t ion @@ @ notes: 1. don't care bit 2. 2nd de vice address code (#) should be same as 1st (@). de vice address de vice address 1st memor y address (n) 2nd memor y address (n) read data (n) 128k 10 10 ## # 10 10 r w a12 a11 a13 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop star t star t ac k ac k no a c k ac k r/w ac k r/w * 1 * 1 dumm y wr ite current address read de vice address read data (n+m) read data (n) read data (n+1) read data (n+2) 128k 10 10 r d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 stop star t ac k ac k no a c k ac k r/w ac k sequen t ial re ad : sequential rea d s a r e initiated by either a c u rrent addre ss rea d or a ra ndom read. if the eeprom receive s ack now ledg m e n t ?0 ? af ter 8-bit r ead data, t h e rea d a d dress is increm ented and t h e ne xt 8 - bi t rea d dat a ar e com i ng o u t . this ope ration can be c ontinued as long as t h e eeprom receives ac knowledgm e nt ?0?. the a d dress will roll ove r a n d returns addre s s zero if it reaches the last a d dress of t h e last page . the sequential rea d ca n be c ontinue d after roll ove r. the se quential read is term inated if t h e ee prom recei ves acknowledgm e nt ?1 ? (no ac knowle dgm ent) a n d a following st op co n d i t i on. sequential read operation r10ds 0 0 06ej 010 0 rev.1.00 page 1 3 of 16 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a notes da ta protection at v cc on/off whe n v cc is t u rn ed o n or o ff, no ise on th e scl and sda i n pu ts ge nerate d by exte rnal c i rcuits (cpu, e t c) m a y act as a t r i gge r a n d t u r n t h e eepr o m t o uni nt ent i onal p r o g ram m ode . to p r even t th is un in ten tio n a l prog rammin g , th is eepr o m has a p o we r o n re s e t fu nct i o n. b e caref ul of t h e n o t i ces desc ri bed bel o w i n o r de r fo r t h e p o w er o n reset function to ope r ate correctly. ? sc l an d sd a sh oul d be fi xe d t o v cc or v ss du ri n g v cc on /off. low to h i gh o r h i g h to lo w tran sitio n d u ring v cc on/ of f m a y cause t h e t r i gge r f o r t h e u n i n t e nt i onal p r o g ram m i ng. ? v cc should be turned off after the ee prom is placed in a s t andby state. ? v cc shou ld b e tu rn ed on f r o m th e g r ou nd level( v ss ) i n o r d e r for th e eepr o m n o t t o en ter th e un in ten tion a l pr o g ram m i ng m ode. ? v cc tu rn on rate shou ld b e sl ower th an 2 s/v. noise suppr ession time thi s ee pr om ha ve a n o i s e s u p p r essi o n fu n c t i on at sc l a n d s d a i n put s , t h at c u t n o i s e of wi dt h l e ss t h an 10 0 ns . b e caref ul n o t t o a l l o w noi se o f wi dt h m o re t h a n 10 0 ns . r10ds 0 0 06ej 010 0 rev.1.00 page 1 4 of 16 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a packag e dimensions r1ex24 128 bsas0a (prs p0008 df -b / prev ious co de: fp-8 dbv) a l e c 1 b 1 d e a 2 b p c x y h e z l 1 4.89 1.06 0.25 0 8 6.02 0.15 0.20 0.25 0.45 0.102 0.14 0.254 3.90 0.406 0.60 0.889 1.73 reference symbol dimension in millimeters min nom max 5.15 a 1 0.35 0.40 6.20 5.84 1.27 0.10 0.69 index mark e 1 y xm p * 3 * 2 * 1 f 4 85 d e h a z b p terminal cross section ( ni/pd/au plating ) b c detail f 1 1 l l a note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. e p-sop8-3.9x4.89-1.27 0.08g mass[typ.] fp-8dbv prsp0008df-b renesas code jeita package code previous code r10ds 0 0 06ej 010 0 rev.1.00 page 1 5 of 16 aug. 04, 20 10
r1ex24 128 bsas0a/ r 1e x2412 8bt a s0a r1ex24 128 btas0 a (pts p0008 jc-b / prev ious co de: ttp-8 dav) a l e c 1 b 1 d e a 2 b p c x y h e z l 1 3.00 1.00 0.13 0 8 6.40 0.10 0.15 0.20 0.25 0.03 0.07 0.10 4.40 0.40 0.50 0.60 1.10 reference symbol dimension in millimeters min nom max 3.30 a 1 0.15 0.20 6.60 6.20 0.65 0.10 0.805 * 1 85 e * 2 index mark 14 * 3 p m x y f a d e h z b detail f 1 1 a l l p terminal cross section ( ni/pd/au plating ) c b note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. e p-tssop8-4.4x3-0.65 0.034g mass[typ.] ttp-8dav ptsp0008jc-b renesas code jeita package code previous code r10ds 0 0 06ej 010 0 rev.1.00 page 1 6 of 16 aug. 04, 20 10
all trademarks and re gistere d trademarks ar e t he propert y of their respectiv e o w n e rs. revision histor y r1ex 24128bsas0a/ r1ex24128bta s0a data sheet de s c ription re v . d a t e p a g e s u m m a r y 1.00 aug. 04, 20 10 initial issu e c - 1
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